1. Field of the Invention
The present disclosure generally relates to the field of semiconductor manufacturing, and, more particularly, to patterning techniques for forming device features having critical dimensions less than the resolution of optical lithography techniques.
2. Description of the Related Art
Semiconductor devices, such as advanced integrated circuits, typically contain a very large number of circuit elements, such as transistors, capacitors, resistors and the like, which are usually formed in a substantially planar configuration above an appropriate substrate having formed thereon a semiconductor layer. The fabrication of semiconductor devices, such as integrated circuits, requires tiny regions of precisely controlled size to be formed in one or more material layers provided above the substrate, such as a silicon substrate, a silicon-on-insulator (SOI) substrate, or other suitable carrier materials. These tiny regions of precisely controlled size are typically defined by patterning the material layer(s) by applying lithography, etch, implantation, deposition processes and the like, wherein, typically, at least in a certain stage of the patterning process, a mask layer is formed over the material layer(s) to be treated to define these tiny regions. Generally, a mask layer may consist of or may be formed by means of a layer of photoresist that is patterned by a lithographic process, typically a photolithography process. During the photolithography process, the resist is spin-coated onto the substrate surface and then selectively exposed to radiation, typically ultraviolet radiation, through a corresponding lithography mask, such as a reticle, thereby imaging the reticle pattern into the resist layer to form a latent image therein. After developing the photoresist, depending on the type of resist, positive resist or negative resist, the exposed portions or the non-exposed portions are removed to form the required pattern in the layer of photoresist. Based on this resist pattern, actual device patterns may be formed by further manufacturing processes, such as etch, implantation, anneal processes, and the like. Since the dimensions of the patterns in sophisticated integrated semiconductor devices are reduced with every new device generation, the equipment used for patterning device features have to meet very stringent requirements with regard to resolution and overlay accuracy of the involved fabrication processes. In this respect, resolution is considered as a measure for specifying the consistent ability to print minimum images of device features under conditions of predefined manufacturing variations. One important factor in improving the resolution is the lithographic process, in which patterns contained in the photo mask or reticle are optically transferred to the substrate via an optical imaging system. Therefore, great efforts are made to steadily improve optical properties of the lithographic system, such as numerical aperture, depth of focus and wavelength of the light source used.
The resolution of the optical patterning process may, therefore, significantly depend on the imaging capability of the equipment used, the photoresist materials for the specified exposure wavelength and the target critical dimensions of the device features to be formed in the device level under consideration. For example, gate electrodes of field effect transistors, which represent an important component of modern logic devices, may be 40 nm and even less for currently produced devices, with significantly reduced dimensions for device generations that are currently under development. Similarly, the line width of metal lines provided in the plurality of wiring levels or metallization layers may also have to be adapted to the reduced feature sizes in the device layer in order to account for the increased packing density. Consequently, the actual feature dimensions may be well below the wavelength of currently used light sources provided in current lithography systems. For example, currently in critical lithography steps, an exposure wavelength of 193 nm may be used, which, therefore, may require complex techniques for finally obtaining mask features having dimensions well below the exposure wavelength. Thus, highly non-linear processes are typically used to obtain dimensions below the optical resolution. For example, extremely non-linear photoresist materials may be used, in which a desired photochemical reaction may be initiated on the basis of a well-defined threshold so that weakly exposed areas may not substantially change at all, while areas having exceeded the threshold may exhibit a significant variation of their chemical stability with respect to a subsequent development process. The usage of highly non-linear imaging processes may significantly extend the capability for enhancing the resolution for available lithography tools and resist materials.
With the ongoing shrinkage of the critical dimensions of the circuit elements, however, the resolution of the patterning process based on sophisticated lithography techniques is substantially based on sophisticated etch techniques based on specifically designed mask layer stacks in combination with specific etch recipes. With reference to FIGS. 1a-1c, a typical sophisticated patterning regime may now be described with reference to forming contact openings so as to extend through an interlayer dielectric material and connect to a semiconductor region, such as a drain and source region of closely spaced transistor elements. It should be appreciated, however, that similar patterning strategies may generally be applied upon patterning any material layer during the fabrication of complex semiconductor devices.
FIG. 1a schematically illustrates a cross-sectional view of a semiconductor device 100 in an advanced manufacturing stage in which contact elements are to be formed so as to connect to critical device areas in a semiconductor material. As illustrated, the semiconductor device 100 comprises a substrate 101, above which is formed a semiconductor layer 102, such as a silicon layer, which in turn comprises a plurality of active regions, i.e., semiconductor regions, in and above which transistor elements are to be formed. For convenience, a single active region 102A is illustrated in FIG. 1a and represents a semiconductor region, above which a plurality of gate electrode structures 110 are formed. As discussed above, the gate electrode structures 110 may represent closely spaced circuit elements 110A, 110B, 110C which have critical dimensions of 50 nm and less so that a spacing between the gate electrode structures 110 may be the same order of magnitude. The gate electrode structures 110 have any appropriate configuration, for instance these structures may comprise a gate dielectric material 112 in combination with an electrode material 111. Furthermore, frequently, a spacer structure 113 is provided in the form of an oxide material, a nitride material and the like. Corresponding contact regions 102C may be formed in the active region 102A between the closely spaced gate electrode structures, at least some of which have to be contacted by corresponding contact elements 125A, 125B, indicated as dashed lines, which have to be formed during the further processing of the device 100 by patterning the dielectric material 121 of a contact level 120.
The semiconductor device 100 may be formed on the basis of any appropriate process strategy which may include sophisticated lithography techniques, etch processes, deposition techniques, anneal processes and planarization processes in order to form any isolation regions (not shown), which in turn laterally delineate the active region 102A. Thereafter, the gate electrode structures 110 are formed by depositing a gate layer stack in combination with hard mask materials and the like, wherein lithography techniques may be applied so as to provide a resist mask, which may then be further shrunk upon specific trim etch processes in order to obtain the desired lateral dimensions of the gate electrode structures. Thus, for providing appropriate mask features for covering the material layer stack and removing an exposed portion thereof, the finally obtained critical dimensions may critically depend on the trim etch processes in combination with the subsequent anisotropic etch strategies. Next, any further processes may be performed so as to form drain and source regions and the contact regions 102C, followed by the deposition of the dielectric material 121, which may represent a complex material system and the like, depending on the overall process and device requirements.
FIG. 1b schematically illustrates a cross-sectional view of the semiconductor device 100 in a further advanced manufacturing stage. As shown, a stack of mask layers 130 is formed above the dielectric material system 120 and comprises a resist layer 131, followed by an anti-reflective coating (ARC) layer 132 and a planarization layer 133. This layer system is patterned on the basis of sophisticated lithography techniques in which the resist material 131 is exposed on the basis of a lithography mask in order to form a latent image in the resist material 131, as is also discussed above. Hence, after development of the resist material 131, mask openings 131A define the lateral position of contact openings 121A to be formed in the material system 120, while, however, the lateral size of the openings 131A may be significantly greater compared to the desired target width of the openings 121A. Consequently, based on the openings 131A, the ARC layer 132 is typically patterned by using appropriate etch strategies, wherein, frequently, the process parameters of the etch process are selected such that corresponding openings 132A in the ARC material have a pronounced degree of tapering in order to further reduce the width. Consequently, the reduced width of the openings 132A at the bottom thereof may be used as an efficient etch mask for patterning the planarization layer 133 in order to form openings 133A therein, which may finally be used as an etch mask for etching into and through the material system 120. It turns out, however, that generally the width 133A may not substantially correspond to the desired target width of the openings 121A, thereby finally generating these openings with an increased width, which in turn may result in device failures or which may require an adapted device design in order to take into consideration the corresponding resolution capability of the patterning process for forming the openings 121A. For this reason, frequently, the etch parameters of the process for forming the contact openings 121A may also be adjusted so as to obtain a certain degree of tapering. It is well known, however, that plasma assisted anisotropic etch recipes rely on process parameters, such as plasma power, reactive components in the plasma atmosphere, polymer residues and the like, which may affect the finally achieved vertical and lateral etch rate. For example, upon increasing directionality and kinetic energy of ions that are present in the etch atmosphere, a pronounced reduction of the lateral etch rate may be achieved. Moreover, adding specific polymerizing gas components may also provide a mechanism for controlling the lateral etch rate since any such polymerizing gas components may result in a more or less pronounced generation of etch byproducts, which preferably accumulate at the sidewalls of the openings 121A. It is to be noted, however, that generally the degree of controllability of the lateral etch rate may also significantly depend on the material composition of the base material to be etched so that generally a very limited range for modulating the lateral dimensions of sophisticated openings, such as the contact openings 121A, is available during a corresponding etch process. For example, silicon dioxide, which is a well-established dielectric material for passivating critical circuit elements, such as the gate electrode structures 110, may allow only a very moderate degree of tapering during the plasma assisted etch process so that it is very difficult to achieve the desired reduced lateral dimensions.
FIG. 1c schematically illustrates the semiconductor device 100 in a further advanced manufacturing stage. As illustrated, the contact elements 125A, 125B comprise an appropriate conductive material 126 and thus electrically contact the contact regions 102C. However, as indicated by the dashed lines, the actual contact elements 125A, 125B may have significantly greater lateral dimensions, thereby possibly contributing to increased yield loss, for instance by forming leakage paths or short circuits in critical areas 114.
In other strategies, the capabilities of the patterning strategies may be enhanced by forming a liner material in the corresponding openings, such as the contact openings 121A (FIG. 1b) in order to appropriately adjust the lateral dimensions, which, however, may require sophisticated deposition and patterning strategies in a very advanced stage of the overall pattering process. Moreover, frequently, corresponding deposition processes and the subsequent patterning may be less than desirable in view of the finally obtained material characteristics, for instance if the patterning of sensitive low-k dielectric materials in metallization layers is considered.
The present disclosure is directed to various methods that may avoid, or at least reduce, the effects of one or more of the problems identified above.